Adapting NWP codes to Accelerators at NCEP, early status

John Michalakes
11 am, Friday 6 Dec, room 2155


Work began in September to port and optimize the NEMS/NMMB model to fine-grained parallel architectures such as the Intel Xeon Phi, a two-Teraflop/s (10^12 floating point operations per second) peak many core co-processor. To date the NEMS/NMMB model has been ported to Phi along with supporting libraries including ESMF and the NCEP libraries. Performance has been measured on a baseline configuration and test data set and work has now begun to identify and optimize the most expensive components within the model. This presentation will provide a status report and an opportunity to help develop strategy, both near and longer term, for position the NCEP operational models to take advantage of increased performance through fine-grained parallel architectures while fostering programmer productivity.